Oana AMĂRICĂI-BONCALO, Public Dissertation of Habilitation Thesis
Thesis Title: "Layered LDPC Decoding Architectures: bridging the Gap from Algorithms to Implementations”
Author: Dr. Eng. Oana AMĂRICĂI-BONCALO
- Chair: Professor Dr. Eng. Adina Magda FLOREA (Politehnica University of Bucharest)
- Professor Dr. Eng. Sergiu NEDEVSCHI (Technical University of Cluj-Napoca)
- Professor Dr. Eng. Mircea POPA (Politehnica University of Timisoara)
This thesis presents the research and academic achievements during the 2013-2019 period.
Modern communication and storage standards require efficient Forward Error Correction (FEC). Due to their excellent error correction capability, Quasy-Cyclic Low-Density Parity-check codes (QC-LDPC) are a class of codes employed in wireless standards, digital video broadcasting, and non-volatile semiconductor memories. This fact prompted the research direction we have pursued during the last 5 years, mainly the study of QC-LDP C decoder architecture trade-offs and optimizations. More specifically, within the framework of the project DIAMOND - Message Passing Iterative Decoders based on Imprecise Arithmetic for Multi-Objective Power-AreaDelay Optimization -, in collaboration with researchers from CEA-LETI Grenoble (dr. Valentin Savin), and ENSEA Cergy-Pont0ise (prof. David Declercq), we have tried to exploit the advantages of implementing imprecise operations in Low-Density ParityCheck (LDP C) decoder architectures, in order to optimize the cost/ area/power consumption. The original project goals to develop hardware architectures that use imprecise arithmetic — have been largely expanded due to the very favorable research results. The contributions presented in this thesis closely follow the DIAMOND project.
The DIAMOND project yielded successful collaborations and high quality research output; at the same time, it also laid the foundations for new research directions such as probabilistic decoding, design and verification of families of hardware architectures, fault tolerant design, etc.